Verilog
2-to-1 Multiplexer
Select between two data inputs with a single control line.
Full Adder
1-bit binary adder with carry-in and carry-out logic.
7-Segment Decoder
Convert 4-bit hexadecimal inputs into 7-segment display patterns.
4-bit Counter
4-bit up counter featuring asynchronous active-high reset.
Universal Shift Register
4-bit register supporting hold, shift right, shift left, and parallel load.
LFSR (Pseudo-Random)
8-bit Galois Linear Feedback Shift Register pseudo-random generator.
PWM Generator
Pulse-width modulation module with dynamic duty cycle control.
4-to-1 Multiplexer by Module Instantiation
Structural 4-to-1 mux built from three 2-to-1 mux instances.
Splitting a Vector
Slice an 8-bit bus into 4-bit, 2-bit, and single-bit outputs.
SystemVerilog
4-function ALU
Arithmetic Logic Unit supporting ADD, SUB, AND, and OR operations.
Parameterized Counter
Flexible width up-counter implementation in SystemVerilog.
Traffic Light FSM
Finite state machine controlling sequential red, yellow, and green lights.
Vending Machine FSM
Coin-operated state machine dispensing items and calculating nickel return.
UART Transmitter
Standard 8N1 serial UART transmitter with configurable clock divider.
SPI Master
SPI Mode 0 bus controller with full-duplex MOSI/MISO transfer logic.
Synchronous FIFO
First-in first-out circular buffer memory with full and empty flags.